This invention relates to demodulation of a class of M-ary PSK signals, and more particularly, to apparatus and methods for demodulating a large class of digital phase shift keyed modulated signals wherein phase change is limited to adjacent phase states.
Digital phase shift keyed signals (PSK signals) find wide application in communication. The signals are produced by discrete changes in phase of a periodic waveform. Phase is changed in accordance with a serial digital data stream acting as a control signal. The present invention has particular application to PSK signals wherein modulation is limited to phase transitions between adjacent phase states.
Prior art PSK modulation schemes have required demodulators whose complexity is proportional to the complexity of the modulated signal. For example, a binary PSK signal requires a relatively simple demodulator consisting of a single channel with a single multiplier used in connection with a local phase reference. A quadrature phase shift keyed (QPSK) signal on the other hand, has in the past required two phase references and two multipliers. As the number of phases increases, so also does the complexity of the circuitry which is used to synchronize the locally-generated phase reference. The locally-generated reference takes a finite time to become synchronized, which causes the first portion of a message to not demodulate properly during burst mode transmission. Such circuitry is complex and potentially expensive, but in the past has been necessary to provide a sufficient margin in the required signal-to-noise ratio for a given bit-error rate.
FIG. 1 shows a typical prior art bipolar phase shift keyed (BPSK) demodulator 10 suitable for demodulating burst mode BPSK transmissions. Referring to FIG. 1, a demodulator 10 employs a phase splitter 12 providing as two outputs a first phase component .theta..sub.1 and a second phase component .theta..sub.2, wherein the second phase component is provided through a short delay line 14 (providing a nominal delay of one bit period), the output of the first phase component and the second phase component being mixed together in a mixer or multiplier 16 to produce a baseband bit stream to be directed through a lowpass filter 18. The output of the lowpass filter 18 is suitable for application to a two-level comparator 20, which is used to produce a stream of ones and zeroes as a digital output.
Quadrature phase shift keyed modulation has required more complex demodulators. An example is found in the textbook Digital Communications--Satellite/Earth Station Engineering, by Kamilo Feher, (Prentice-Hall, 1983), pp. 170-171. Therein is described a differential offset QPSK demodulator and a differential QPSK demodulator. In this demodulator, the in-phase (I) output and the quadrature-phase (Q) output are separately converted into digital levels before recombination into a serial data stream. The recombination requires a priori knowledge of the bit clock phase. This demodulator only works for QPSK signals. It is believed that there have never before been such simple demodulators for higher order M-ary PSK signals.
What is needed is a simple demodulator for QPSK which eliminates ambiguity of reinterleaving the signals and which can be used with M-ary PSK signals in situations where signal-to-noise ratio is not a primary consideration and which can also produce valid data with minimal delay from the start of transmission.